1. Field of the Invention
The present invention relates to computer systems and, more specifically but not exclusively, to using cache memory to store and retrieve data in computer systems.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) protocol, from Advanced RISC (Reduced Instruction Set Computer) Machine (ARM), of Cambridge, England, defines the interface between a master device, such as a cache, and a slave memory. The protocol includes an address from the cache to the memory that is coupled with an identification (ID) value. The data retrieved from the memory to the cache is coupled with the same ID value. The cache, or an arbiter, uses the ID value to differentiate between different masters that access a common slave memory such that the use of ID values enables interleaving of multiple accesses to the memory by the different masters.
The management of multiple read accesses (i.e., requests for data) by a cache involves tracking the accesses by keeping the addresses of the accesses (or the cache line numbers associated with these addresses) in the cache and coupling the addresses with the different sets of data returning from the memory. The kept addresses are used to direct the data coming from the memory into the correct locations (e.g., cache lines) in the cache, and also to compare the addresses to successive accesses to the same address, e.g., to detect when an address is already in service for a request that has not yet been completed (i.e., data is on the way). The protocol assures that back-to-back requests with the same ID number result in returned data in order. Nevertheless, using different ID numbers allows out-of-order returned data, which can also be interleaved. With this character of the protocol, the cache might use one of the following options:                1. Use only a single ID number and support one or more requests from memory. In that case, the data is assumed to be returned in order, and the cache should maintain a FIFO buffer in order to direct the returned data into the appropriate cache line. In this structure, the cache must include a number of buffers keeping addresses or cache line numbers equal to the number of requests it supports.        2. Use a few ID numbers and support several requests from memory. In that case, the data can be returned out of order, and the cache should maintain a management buffer in order to direct the returned data into the appropriate cache line. In this structure, the cache must include a number of buffers keeping addresses or cache line numbers equal to the number of requests it supports.        3. There is also an option to combine the two approaches above, where the cache uses a FIFO of buffers for each ID number it uses. Still, the cache must have as many buffers as the number of supported requests.        
Maintaining a specific number of address buffers for different requests (interleaved or non-interleaved) limits the computer system to that specific number as the maximum number of different requests that the cache can handle. When all of the address buffers are occupied, the next request will pend, and the system will stall. In order to increase the number of different requests that the cache can handle, more address buffers have to be provisioned, which leads to increases in the area, power consumption, timing, complexity, and cost of the cache module.